MOSFETs are vulnerable to ESD voltages as a consequence of the environment in which they operate. This vulnerability is due to the thinness of the gate oxide layer of the MOSFET device. The thinness of the layer is a desired necessity for achieving fast MOSFET devices. Typically, a conventional MOSFET device will have a gate oxide thickness of approximately 60 Angstroms, resulting in an oxide breakdown voltage of approximately 5 to 6 volts. ESD voltages may easily reach several hundred volts, however, and such ESD voltages can severely degrade--if not destroy--the affected MOSFET device.
Furthermore, as a result of the continued scaling and shrinking of semiconductor devices, IC chips have progressively become smaller and denser. To facilitate these highly integrated semiconductor devices, the typical supply voltage of 5 volts has been reduced to a voltage level less than 5 volts, commonly from about 3.6 volts to as low as 2.5 volts.
Often a mix of ICs is used on the same printed circuit (PC) board. Some of the ICs are designed to use a standard supply of 5 volts and other ICs on the PC board are designed to use a much lower voltage level. This mix creates a problem of possible overvoltage conditions, when a voltage level higher then the supply voltage level of the IC is presented at the pad of that IC. When a high-voltage IC feeds into a low-voltage IC, the low-voltage IC may encounter excessive voltage stresses in the thin oxide layers of some of the semiconductor devices in the circuitry interfacing between the ICs.
Pass transistors have been designed to handle overvoltage conditions and to protect receiver circuits. Such a circuit is shown in FIG. 1. As shown, prior art circuit 10 comprises pass transistor 14, which is an n-channel MOSFET, connected between pad 24 and receiver 18. The gate of pass transistor 14 is coupled to supply voltage 12, V.sub.DD. Receiver 18 also has the drain of keeper MOSFET 16, which is a p-channel MOSFET, connected to its input node 26. Output node 20 of receiver 18 is coupled to the gate of keeper MOSFET 16. The source of keeper MOSFET 16 is coupled to supply voltage 12. To those familiar with the art, keeper MOSFET 16 may also be referred to as a boost transistor or half-latch transistor.
Generally, a high signal voltage level is at about V.sub.DD and a low signal voltage level is at about V.sub.SS, or ground. In normal operation, when supply voltage V.sub.DD is "on," a high signal voltage level at pad 24 generates a "weak" high at node 26. The "weak" high is caused by the threshold voltage drop across the input and output sides of pass transistor 14. The voltage level may be brought back up to V.sub.DD at node 26 by keeper MOSFET 16. A low signal level at node 20 turns on p-channel MOSFET 16, which then latches node 26 to V.sub.DD. Consequently, any overvoltage condition at pad 24 is absorbed by the threshold voltage drop across the pass transistor 14.
Because node 26 is latched to V.sub.DD when MOSFET 16 is on, an overvoltage condition or an ESD condition at pad 24 stresses pass transistor 14. Furthermore, an ESD condition at pad 24 stresses pass transistor 14 even when MOSFET 16 is off. During its off state, n-well 22 is at V.sub.DD potential and the drain of MOSFET 16 at node 26 is at a single diode voltage drop away from V.sub.DD. When node 26 rises one diode voltage drop above n-well 22, node 26 is effectively pinned to a voltage potential of V.sub.DD plus one diode voltage drop. The pinning of node 26 stresses pass transistor 14 during an overvoltage or ESD condition at pad 24.
Stress problems potentially exist even when the circuit of FIG. 1 is unpowered. If V.sub.DD is at ground potential, node 26 is pinned, nevertheless, to a voltage potential of one divide voltage drop above ground potential. Again, an ESD condition at pad 24 may stress pass transistor 14. From the above discussion, it is seen that an improved receiver circuit that is tolerant to overvoltage and ESD conditions is needed.